Xbox 2 Already Patent?

Teamxbox reports earlier, the Xbox 2 has had a patent on its upcoming module. You all may wonder, “Why the patent?” Well, Teamxbox has covered the information with J Allard in a previous interview.

Here’s the patent information and details preserved for press provided by Teamxbox:

The patent not only exposes a real-life implementation of this “procedural synthesis” technique but also corroborates some of the leaked Xbox 2 specs.

The patent relates to a “System and method for parallel execution of data generation tasks,” which in layman terms refers to specialized hardware that uses different processing units to simultaneously perform a series of tasks. The system described in the patent can be implemented on any kind of platform and the document mentions both the PC and Microsoft’s Xbox as examples.

To our surprise, the first drawing in the patent looks almost identical to some of the leaked Xbox 2 schematics that were released last year:

The patent describes a system comprising of a CPU module (102), a GPU module (104) and some additional components, but focus mostly on the interaction between the CPU and GPU modules.

The CPU module, which basically acts as a multi-core chip, has different CPUs and the system can assign different functions to each core. In one of the implementations, CPU 1 is a Host processing unit while the other CPUs act as “geometry processing” units. The following is an example application mentioned in the document: (check the above drawing for references)

In a typical gaming application, the host CPU 1 (108) performs the high-level tasks associated with the game, such as receiving a player’s input, performing scene management, performing the computations used to simulate the physical phenomena represented by the application, performing any artificial intelligence provided by the game, and so on. The CPUs 2 to n (110, . . . 112) perform more fine-grained processing associated with a game.

This basically means that the host CPU (108) plays a similar role to what a CPU does in current consoles; the CPU handles the game code and everything related to game physics, AI, etc. In the next generation, the computational power will be big enough to handle traditional tasks run by the CPU and still have available resources for other types of tasks. The following is the description to what is specifically the new invention patented:

In one application, these CPUs (110, . . . 112) generate geometry data associated with one or more objects in the scene. For instance, as will be described, each of these processors may include logic for performing procedural geometry. Such logic receives input data defining tasks to be performed, and then executes such tasks to provide output geometry data (e.g., a collection of vertices). To provide merely one example, a game designer could provide procedural logic to generate geometry data associated with individual leaves on a tree. Such procedural logic would receive a relatively limited amount of information associated with such a task, such as a location of an individual leaf, a direction of any simulated wind in the scene, and so on. Based on this information, the procedural logic could generate vertices that define an individual leaf on the tree. The CPUs that perform geometry-related tasks are referred to as geometry-generating CPUs.

This last paragraph sounds a lot like the “procedural synthesis” techniques that Allard discussed last year. Then, the paper gives other potential applications such as the generation of higher-order surfaces, LOD processing and even GPU commands, which means that a CPU could run code that is originally meant to be executed by the GPU.

The diagram, and the different examples described in the patent, also confirm information revealed in the Xenon white paper leaked last year that claimed that “the Xbox Advanced Technology Group (ATG) is also exploring a variety of techniques for offloading graphics work to the CPU.”

Finally, the patent continues describing the interaction between both modules and the necessary hardware and programming instructions to avoid bottlenecks and take maximum advantage of the system’s bandwidth to handle the geometry data between the CPU and GPU modules.